The present invention relates to the transfer of data, for example the transmission of multiple data messages over a single transmission medium and the conversion of those messages into a form suitable for transmission.
There is a growing market in the field of digital communication. An increasing number of households have equipment to receive digital television, satellite and cable television, telephony and internet services. Telephony systems and the internet are interactive systems over which people can send and receive information and other digital communication systems are increasingly tending towards interactivity, for example as video-on-demand systems are introduced.
Video, audio and other information (e.g. internet services), all hereinafter referred to as xe2x80x9cdataxe2x80x9d, can be transmitted along a number of transmission media, for example over electrical or optical cable or via radio. The data can be considered to be made up of xe2x80x9cmessagesxe2x80x9d, each message being, for example, one television channel or one internet connection. To allow a plurality of messages to be sent over a single transmission channel one approach is to split the messages into parts at the transmission device, transmit each part over the transmission channel and then recombine the parts at the receiving device to reconstitute the message. Each message is thus contained in a number of parts, which can arrive at the receiving device over a period of time. Additional information can be transmitted with each segment, for example to indicate the message of which the segment forms part. Consecutively sent messages need not then form part of the same message since the receiving device can use the additional information to allow it to recombine segments of each message with each other.
One system that uses this principle is AAL5. In this system data is transmitted in the form of asynchronous transfer mode (ATM) xe2x80x9ccellsxe2x80x9d of 53 bytes in length, of which the first 5 bytes constitute the additional information mentioned above and the other 48 bytes constitute the segment of the message. By convention each byte consists of 8 bits.
The messages themselves may be split into higher-level parts before they reach the transmission stage: for example video data can be in the form of MPEG frames.
One practical embodiment of a personal system for handling data in this form is a set-top box. This usually receives a digital data feed, forms the received data into digital messages, performs the necessary digital-to-analogue conversion and final backend processing of the messages and outputs signals suitable for use by other apparatus such as televisions, telephones or internet terminals. There is also normally provision for transmission of information (normally at a lower data rate) in the opposite direction to allow a user to operate interactive services. The reverse data can conveniently, although not necessarily be sent in the same format as the forward data.
In order to meet the demands of consumers for high data rate services such as video a set-top box should preferably be capable of receiving and transmitting at a rate of at least 1 to 10 Mbits/s and preferably of receiving at least 50 Mbits/s. This imposes very heavy demands on the processing systems that are to perform the transmitting and receiving operations, especially the segmentation of messages into parts and the reassembly of those parts. Since the set-top box is intended as a consumer product there is a particular need to provide a device for performing the transmitting and receiving operations that is as inexpensive as possible.
There are known integrated circuit systems that can perform the segmentation and re-assembly (xe2x80x9cSARxe2x80x9d) functions described above for use in a personal system. Current systems fall generally into two categories, having the following characteristics:
Hardware-based designs
Very fast dedicated SAR engines (typically 155/622 Mbits/s)
Large silicon areas
Expensive, and although they are hardware-based systems they often still require a microprocessor for control purposes
Complicated control registers and memory management data structures defined in hardware
Inflexible, which makes it difficult to adapt them to rapidly evolving new standards and markets
Software/Processor-based designs
Relatively slow (usually sub 20 Mbits/s)
Can be inexpensive with cheap RISC (reduced instruction set computing) processors, but become uneconomic in embedded situations at high data rates (40-50 Mbits/s upwards) because expensive high performance processors are needed
Flexible, as all control and data structures are software-defined, so easier to modify as standards evolve
In fact, there are four conflicting design requirements which need to be met for widespread consumer use:
Cost Targets. To a large extent the cost of an integrated circuit SAR engine is determined by the complexity of the circuit and the die area it occupies. Known hardware-based systems generally occupy large areas and whilst low-cost RISC software-based systems are cheaper to produce, their performance is modest.
Flexibility to meet evolving standards. Hardware-based systems are generally inflexible.
Performance targets. Existing hardware-based solutions have high performance but are too expensive for many consumer applications. Existing software-based solutions are cheaper but have modest performance.
Ease of Interfacing to other parts of the system
It is clear from the above analysis that the SAR engines currently available do not provide an effective technical and cost-effective solution.
According to a first aspect of the present invention there is provided a data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising:
a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer;
a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and
a data storage controller for receiving, for each received amount of data, the identity portion of the amount of data and performing a storage operation comprising:
accessing the first storage information memory; and
if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the data stream storage area corresponding to that data stream; and
if the first storage information memory does not hold first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the escape buffer; and
a processing unit connected to the escape buffer for performing an assembly operation comprising executing steps to assemble the information stored in the escape buffer into respective data streams.
Preferably the data storage controller and the processing unit are operable in parallel. Preferably the storage operation is a hardware operation and/or the assembly operation is a software operation.
The escape buffer is suitably a buffer provided in one or more memories.
The data storage controller and the processing unit are preferably provided on a single integrated circuit. The integrated circuit may include memory. The processing unit is preferably the central processing unit (CPU) of the integrated circuit.
The data reception unit preferably comprises a second storage information memory for storing, for a plurality of the data streams, second storage information for enabling storage of data from a respective data stream. Each second storage information preferably comprises first pointer information usable as a pointer to the respective data stream storage area.
Preferably each first storage information comprises second pointer information usable as a pointer to respective second storage information in the second storage information memory. Preferably each first storage information comprises an identity code for the respective data stream. Each identity code may be associated with the respective second pointer information.
The data storage controller is preferably arranged to access, in the storage operation, the second storage information memory by means of the first storage information to retrieve first pointer information, store the data portion of the said amount of data at a location in the data stream memory indicated by the first pointer information, and increment the first pointer information by a value representing the length of the data portion.
At least some of the second storage information is preferably stored in the second storage memory in equally spaced blocks, each block holding the second storage information for a single data stream. At least some of the blocks may alternatively not be equally spaced.
The second pointer information is preferably usable as a pointer to the location in the second storage information memory of respective second storage information by multiplying the second pointer information by a value representing the spacing of the blocks and then adding a predetermined offset to generate the said pointer.
The first storage information memory is suitably a content addressable memory. The second pointer information is then preferably the return value of the content addressable memory.
Preferably, if the first storage information memory does not hold first storage information for the data stream identified by the identity portion the data storage controller stores the data portion of the amount of data together with the identity portion of the amount of data in the escape buffer.
The data storage controller is preferably capable of sending a buffer full signal to the processing unit when the contents of the escape buffer exceed a predetermined size to trigger the processing unit to perform the assembly operation.
The second storage information memory preferably comprises escape pointer information usable as a pointer to the escape buffer.
The data storage controller is preferably arranged to access, in the storage operation, the second storage information memory to retrieve escape pointer information, store the data portion of the said amount of data at a location in the data stream memory indicated by the first pointer information, and increment the first pointer information by a value representing the length of the data portion.
Each amount of data preferably represents an ATM cell. The length of each amount of data is suitably 424 bits.
According to a second aspect of the present invention there is provided a method for receiving a plurality of data streams over a data channel, the method comprising performing the steps set out above in relation to the first aspect of the invention.
The present invention will now be described by way of example with reference to the accompanying drawings in which: